View R2A20111SP_6561412.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rej03f0231-0100 rev.1.00 mar 28, 2007 page 1 of 40 R2A20111SP/dd power factor correction controller ic rej03f0231-0100 rev.1.00 mar 28, 2007 description the r2a20111 is a power-factor correction (pfc) controller ic. this ic adopts continuous conduction mode as pfc operation. various functions such as constant power limit, overvoltage detection, overcurrent detection, soft start, feedback-loop disconnection detection, and holding function of pfc operation through momentary outage (pfc hold function) are incorporated in a single chip. thes e functions reduce external circuitry. the constant power limit function allows to eliminate a significant amount of coil noise which is generated due to overcurrent detection operation in case of conventional overload. the pfc hold function enables quick recovery by continuing pfc operation after momentary outage. the hold time can be adjusted by an external capacitance. overcurrent detection pin is separately provided. latch mode shutdown function is incorporated. a soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage. features ? maximum ratings ? power-supply voltage vcc: 24 v ? operating junction temperature tjopr: ? 40 to 125c ? electrical characteristics ? vref output voltage vref: 5.0 v 3% ? uvlo operation start voltage vh: 10.5 0.9 v ? uvlo operation stop voltage vl: 9.0 0.7 v ? pfc output maximum on duty dmax-out: 95% (typ.) ? functions ? constant power limit function ? continuous conduction mode ? hold function of pfc operation on momentary outage (pfc hold function) ? overvoltage detection ? overcurrent detection ? soft start ? feedback loop disconnection detection ? ic shutdown function ? package lineup: sop-16 and dilp-16 applications ? flat panel display ? projector ? desktop pc ? white goods
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 2 of 40 ordering information part no. package name package code taping spec. R2A20111SPw0 fp-16dav prsp0016dh-b 2000 pcs./one taping product r2a20111ddu0 dp-16fv prdp0016ae-b ? system diagram from out 150 h to q1 gate rec+ rec? b+ q1 1.28m 0.0165 (5w) 680k 2.2k 470p b+ out gnd (385v dc) 470 f 2 (450v) to fb from vrb1(b+ monitor1) vrb1 6800p 1 0.1 720k 24v 680k 4.7 t1 0.47 10k 22k from auxiliary vref vref vref 14k 82k 0.22 62k 390p 1000p gate driver +/? 1.0a (peak) 5v internal bias circuit ground vcc iac cai cao gnd eo cgnd climit out 27.5v 5v vref generator fb 0.1 vref uvl rt b+ovp pfc-off 25 a ss ct v amp fb low pfc-on delay vref good in out c limit c amp imo = k {iac (veo ? 1v)} imo iac veo 2.5v k 1.3 v 0.52v vref good vref delay reset 4.0v vref 1.2v 0.82v 0.79v pfc delay pfc delay in out delay reset shut down rt rt 2.688v 2.638v vref ss gain shut down reset: vcc<4v uvlo h l 10.5v 9.0v 3.6v 0.65v vref 2.4k 0.033 820k 2.4k 100 100p r s q q r s q q r s q q s r q q s r q q 6 1 3 15 2 16 9 10 7 12 5 4 8 14 13 11
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 3 of 40 pin arrangement (top view) 1 2 3 4 5 6 7 8 vcc ss eo fb iac pfc-on ct rt 16 15 14 13 12 11 10 9 out gnd delay cgnd cai vref cao climit pin description pin no. pin name i/o function 1 out output power mos fet gate driver output 2 gnd ? ground 3 delay input/output hold ti me adjust and ic shutdown 4 cgnd input non-inverting i nput of current amplifier 5 cai input/output inverting i nput of current ampl ifier and current out put for pfc control 6 vref output reference voltage output 7 cao output current amplifier output 8 climit input overcurrent detection 9 rt input/output timing resistor for settings of operational frequency, and the maximum cai pin and delay pin current 10 ct output timing capacitor for operational frequency adjust 11 pfc-on input detection of input ac voltage level 12 iac input detection of input ac waveform 13 fb input voltage amplifier input 14 eo output voltag e amplifier output 15 ss output timing capacitor for soft-start time adjust 16 vcc input power supply voltage input description of pin functions out pin: the power mos fet gate-drive signal is output from this pi n, and takes the form of a r ectangular waveform with an amplitude of vcc-gnd. gnd pin: the ground terminal. delay pin: this pin has two functions; (1) setting the pfc function hold time for cases of momentary outage and (2) ic shutdown. current that flows through the delay pin is in inverse proportion to the rt pin resistance. source current is 4.7/rt [a] and sink current is 42.3/rt [a]. normal ope ration is in the state that sink current flows.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 4 of 40 (1) setting the pfc function hold time for momentary outage when the pfc-on pin is driven below 0.79 v (typ.) due to a momentary outage, the delay pin functions as source current. pfc operation continues until the capacitor is char ged to 1.2 v (typ.). after the voltage on the delay pin reaches 1.2 v (typ.), the pin functions as sink current, and pfc operation te rminates. the pfc function hold time can be set by the value of the external capacitor. (2) shutdown when this pin is pulled up to 4 v (typ.) or higher, the ic enters the shutdown state. accordingly, the vref signal becomes low and the operating current becomes several hundred a. the ic does not resume operation until vcc falls to 4 v (max.) or below. cgnd pin: this pin is the non-inverting input to the current amplifier. cai pin: this pin is the inverting input to the current amplifier and functions as source current for pfc control. ac current is controlled to be proportional to the source current and the power factor is corrected. vref pin: temperature-compensated voltage with an accuracy of 5 v 3% is output from this pin. the pin should supply no more than 5 ma (max.) source current. this pin has no sink capabilities. cao pin: this pin is the current amplifier output, and is connected to the phase-compensatio n circuit of the current amplifier. the result of comparison of the voltage on this pin and the ct pin produces the pulse output from the out pin. the pulse is limited when the voltage on the cao pin rises. climit pin: this pin is for detecting overcurrent. when the voltage on this pin drops to 1.3 v (typ.) or below, out pin is stopped. rt pin: this pin is for frequency adjustment of the oscillator and connected to gnd via resistor. the ic operating frequency is determined by this resistance valu e and the ct pin capacitance value. additionally, this resistance value determines the maximum cu rrent on the cai pin and the current on the delay pin. ct pin: this pin is for frequency adjustment of the oscillator and connected to gnd via capacitor. the ic operating frequency is determined by this capacitance value and the resistance value of the rt pin. pfc-on pin: this pin is applied smoothing voltage of rectified ac voltage and detects the input ac voltage level. when 0.82 v (typ.) or more is applied to this pin, pfc operation starts. when the voltage is 0.79 v (typ.) or lower, the pfc operation stops after the pfc operation hold time (refer to the description of delay pin operation). iac pin: this pin is for detecting waveform of the input ac voltage. fb pin: this pin is the input to the voltage amplifier. this pin is applied to voltage divided pfc output with resistors. the feedback loop is intended to keep 2.5 v (typ.). when output voltage rises up and the voltage of this pin is higher than 2.688 v (typ.) or more, the out pin is stopped. moreover, when this voltage of this pin is 0.52 v (typ.) or lower, the out pin is also st opped. these functions detect overvoltage, low voltage, and feedback-loop disconnection.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 5 of 40 eo pin: this pin is the output of the voltage amplifier. this pin is connected to the phase-compensation circuit of the voltage amplifier. ss pin: this pin is connected to gnd or vref via a capacitor. this pin is pulled up to the voltage on the vref pin until pfc operation starts. when the voltage on the pfc-on pin has r eached 0.82 v (typ.), pfc oper ation starts and this pin flows 25 a source current. operation of the cao pin is affected by that of the ss pin, the pulse width of the out pin is limited, and this prevents overshooting when start up. vcc pin: this pin is for the ic power supply. the ic starts up at 10.5 v (typ.), and stops at 9 v (typ.).
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 6 of 40 absolute maximum ratings (ta = 25c) item symbol ratings unit note supply voltage vcc 24 v out peak current ipk-out 1.0 a 3 out dc current idc-out 0.1 a vi-group1 ?0.3 to vcc v 4 terminal voltage vi-group2 ?0.3 to vref v 5 cao voltage vcao ?0.3 to vcaoh v eo voltage veo ?0.3 to veoh v delay voltage vdelay ?0.3 to +6.5 v cai voltage vi-cs ?1.5 to +0.3 v rt current irt ?200 a iac current iiac 0.6 ma vref current io-ref ?5 ma power dissipation pt 1 w 6 operating junction temper ature tj-opr ?40 to +125 c storage temperature tstg ?55 to +150 c notes: 1. rated voltages are wi th reference to the gnd pin. 2. for rated currents, inflow to the ic is indicated by (+), and outflow by (?). 3. the transient current when driving capacitive load. 4. this is the rated voltage for the following pin: out. 5. this is the rated voltage for the following pins: cgnd, vref, climit, rt, ct, pfc-on, iac, fb, ss 6. thermal resistance of packages package ja jc note dip16 120 c/w 50 c/w ? 120 c/w ? 40 40 1.6 [mm], mounted on a glass epoxy printed board with 10% wiring density sop16 ? 35 c/w infinite heat sink
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 7 of 40 electrical characteristics (ta = 25 c, vcc = 12 v, rt = 27 k , ct = 1000 pf) item symbol min typ max unit test conditions start threshold vh 9.6 10.5 11.4 v shutdown threshold vl 8.3 9.0 9.7 v uvlo hysteresis dv uvl 1.0 1.5 2.0 v startup current is 140 200 260 a vcc = 9.5 v is temperature stability dis/dta ? ?0.3 ? %/c * 1 supply operating current i cc 3.45 4.5 6.45 ma iac = 0 a, cl = 0 f output voltage vref 4.85 5.00 5.15 v isource = 1 ma line regulation vref-line ? 5 20 mv isource = 1 ma, vcc = 12 v to 23 v load regulation vref-load ? 5 20 mv isource = 1 ma to 5 ma vref temperature stability dvref ? 80 ? ppm/c ta = ?40 to 125c * 1 initial accuracy fout 58.5 65 71.5 khz measured pin: out fout temperature stability dfout/dta ? 0.1 ? %/c ta = ?40 to 125c * 1 fout voltage stability f out-line ?1.5 0.5 1.5 % vcc = 12 v to 18 v ct peak voltage vct-h ? 3.6 4.0 v * 1 ramp valley voltage vct-l ? 0.65 ? v * 1 oscillator rt voltage vrt 1.17 1.25 1.33 v soft start sink current iss 15.0 25.0 35.0 a ss = 2 v threshold voltage vcl 1.222 1.3 1.378 v current limit delay to output td-cl ? 100 200 ns climit = 2 to 0 v feedback voltage vfb 2.40 2.50 2.60 v fb-eo short input bias current ifb ?0.3 0 0.3 a measured pin: fb open loop gain av-v ? 53 ? db * 1 high voltage veoh 5.2 5.7 6. 2 v fb = 2.3 v, eo: open low voltage veol ? 0.1 0.3 v fb = 2.7 v, eo: open source current isrc-eo ?180 ?120 ?90 a fb = 1.0 v, eo = 2.5 v sink current isnk-eo 90 120 180 a fb = 4.0 v, eo = 2.5 v v amp transconductance gm-v 150 200 290 a/v fb = 2.5 v, eo = 2.5 v note: 1. design spec.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 8 of 40 electrical characteristics (cont.) (ta = 25 c, vcc = 12 v, rt = 27 k , ct = 1000 pf) item symbol min typ max unit test conditions input offset voltage vio-ca ? (?10) 0 mv * 1 open loop gain av-ca ? 68 ? db * 1 high voltage vcaoh 5.2 5.7 6.2 v low voltage vcaol ? 0.1 0.3 v source current isrc-ca ?135 ?90 ?67 a cao = 2.5 v sink current isnk-ca 67 90 135 a cao = 2.5 v c amp transconductance gm-c 530 700 1000 a/v * 1 iac pin voltage viac 1.6 2.3 3.0 v iac = 100 a imo current 1 imo1 ?61.3 ?51.5 ?41 a eo = 2.5 v, iac = 150 a pfc-on = 1.2 v imo current 2 imo2 ?197.9 ?165 ?131.5 a eo = vcaoh, iac = 150 a pfc-on = 1.2 v imo current 3 imo3 ?32.8 ?27 ?21.2 a eo = 2.5 v, iac = 375 a pfc-on = 2.5 v iac/ multiplier imo current 4 imo4 ?110.4 ?92 ?73.6 a eo = vcaoh, iac = 375 a pfc-on = 2.5 v minimum duty cycle dmin-out ? ? 0 % cao = 4.0 v maximum duty cycle dmax-out 90 95 98 % cao = 0 v rise time tr-out ? 30 100 ns cl = 1000 pf fall time tf-out ? 30 100 ns cl = 1000 pf vol1-out ? 0.05 0.2 v iout = 20 ma vol2-out ? 0.5 2.0 v iout = 200 ma (pulse test) low voltage vol3-out ? 0.03 0.7 v iout = 10 ma, vcc = 5 v voh1-out 11.5 11.9 ? v iout = ?20 ma out high voltage voh2-out 10.0 11.0 ? v iout = ?200 ma (pulse test) shut down voltage vshut 3. 30 4.00 4.70 v input: delay reset voltage vres ? ? 4.0 v input: vcc shut down shut down current ishut 120 190 260 a vcc = 9 v note: 1. design spec. c limit c amp iac veo k 1.3v oscillator climit cgnd cai iac cao imo imo = k {iac (veo ? 1v)}
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 9 of 40 electrical characteristics (cont.) (ta = 25 c, vcc = 12 v, rt = 27 k , ct = 1000 pf) item symbol min typ max unit test conditions pfc enable voltage von-pfc 0.74 0. 82 0.9 v input pin: pfc-on pfc disable voltage voff-pfc 0.71 0.79 0.86 v input pin: pfc-on pfc disable delay threshold voltage vd-pfc 1.05 1.20 1.30 v input pin: delay input current ip fc-on ?1.0 ?0.2 1 a pfc-on = 2 v b+ ovp set voltage dvovps 0.125 0.188 0.250 v input pin: fb * 1 b+ ovp reset voltage dvovpr 0.075 0.138 0.200 v input pin: fb * 1 fb low set voltage vfbls 0.425 0.52 0.615 v input pin: fb delay source current isrc-delay ?47.5 ?42.5 ?38 a delay = 1 v rt = 27 k supervisor delay sink current isnk-delay ? 770 ? a delay = 1 v rt = 27 k * 2 note: 1. dvovps = vovps ? vref 0.5 dvovpr = vovpr ? vref 0.5 vovps vovpr fb out vref 0.5 vfbls 2. design spec.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 10 of 40 timing chart 1. startup and stop timing ss cao fb out vref pfc-on 0.82v (von-pfc) pfc-off (internal signal) vcc 10.5v (vh) soft start 5v 4.0v cao ss 9.0v (vl) cao vref good (internal signal) ct
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 11 of 40 2. stop timing by pfc-on pin ss fb out normal control pfc-on 0.79v (voff-pfc) pfc-off ( internal signal ) td-pfcoff delay 1.2v(vd-pfc) pfc hold time
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 12 of 40 3. oscillator, gate drive output ct dead time (internal signal) out ( leading edge control ) cao 4. pfc operation on/off 1.2v(vd-pfc) 0.82v(von-pfc) 0.79v(von-pfc) pfc-on delay pfc-off ( internal signal ) out
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 13 of 40 5. fb supervisor ss fb out b+ovp ( internal signal ) fb low ( internal signal ) 0.52v(fb low) vovpr vovps
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 14 of 40 description of functions 1. uvl circuit the uvl circuit monitors the vcc voltage. when the voltage is lower than 9.0 v, the ic is stopped. when the voltage is higher than 10.5 v, the ic is started. when operation of the ic is stopped by the uvl circuit, the driver circuit output is fixed low, and output of vref and the oscillator are stopped. vref vcc 10.5v (vh) 5v 4.0v ct cao 9v (vl) out figure 1 uvl operation
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 15 of 40 2. operating frequency the r2a20111 operating frequency fosc is determined by adjusting the timing resistor rt (the rt pin, pin 9) and the timing capacitance ct (the ct pin, pin 10). the operating frequency is approximated by the following expression: fosc = 1.755 10 6 rt (k ) ct (pf) (khz) make sure to use a 7 k or more resistance because of the maximum ra ting of the rt-pin. meanwhile, as the resistance increases, the ic will become more susceptible to noise, etc. the resistance, therefore, should be up to about 100 k . also, use a 100 pf or more for the timing capacitance to reduce effects from parasitic capacitance and noise. when the ic is operated at high frequenc ies, the expression becomes less accurate du e to the ic internal delay time, etc. please confirm operation the value with the actually mounted ic. the maximum operating frequency is 400 khz. as a reference, the operating frequency data when the timing resistor and the timing capacitance are changed is shown in the figure below. 1 10 100 1000 110100 timing resistance (k ) timing capacitance ct operating frequency (khz) 470pf 1000pf 2200pf 4700pf figure 2 operating frequency characteristics
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 16 of 40 3. soft start this function gradually increases the pulse width of the out pin from a 0% duty cycle at the startup. by preventing a sudden increase of the pulse width, potentia l problems such as transient stress on the external parts, overshoot of the pfc output voltage (b+ voltage), or coil noise generated due to overcurrent will be prevented. although the duty cycle is controlled by the cao signal, operation of the cao pin is affected by the voltage on the ss pin during the soft start. when the voltage on the cao pin reaches the required voltage level, the soft start ends an d operation transfers to the normal control. the soft-start time can be set by an external capacity. ct out ss cao pfc-on 0.82v ss cao pfc output voltage gate driver +/ ? 1.0a(peak) cao out pfc-on 25 a ss ct 10 7 11 1 15 c amp vref 0.82v 0.79v vref 5 4 cai cgnd vref 14k 1 720k full-wave rectified ac 0.47 vref to power mos fet gate + ? + ? + ? figure 3 soft-start operation waveform
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 17 of 40 4. pfc-on pin function the pfc-on pin is applied smoothing voltage of rectified ac voltage. accordingly, the ac voltage state is detected and each function depending on the power-su pply state is operated. details of their operation are given below. note, however, that the functions do not operate when vref voltage is lower than 4 v as uvl operation and shutdown state. 14k 1 720k pfc-on ? 0.2 5 15 ss 0.82v 0.79v full-wave rectified ac 0.47 vref 0.22 25 a vref delay 3 4.7 rt [a] 42.3 rt [a] vref 1.2v pfc-on/off control multiplier gain selector to power mos fet gate rt gate driver +/? 1.0a(peak) out rt 1 9 vref constant current circuit figure 4 internal circuits connected to the pfc-on pin 4-1. power-supply startup operation when the ac voltage is applied, the voltage on the pfc-on pin rises and the pfc output voltage is charged to about 2 ac voltage. after the voltage on the pfc -on pin exceeds 0.82 v, the voltage of the ss pin starts to be discharged and pfc operation starts. once the pfc operation starts, the pfc output voltage is boosted to the prescribed voltage. full-wave rectified ac pfc-on ss cao ss cao pfc output voltage 0.82v figure 5 waveform in operations in startup
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 18 of 40 4-2. multiplier gain switching multiplier gain is switched according to the input ac voltage. 4-3. operation on a momentary outage (pfc operation hold on momentary outage: pfc hold function) (1) when the momentary outage is short during a momentary outage, the voltage on the pfc-on pin is discharged. when it reaches 0.79 v, charging of the capacitor on the delay pin starts. when ac-voltage input is resumed, and the voltage on the delay pin doesn?t reach 1.2 v before the voltage on the pfc-on pin rises above 0.82 v, the pfc output voltage resumes quickly since the soft-start function is not operated. when the voltage on the pfc-on pin falls below 0.6 v during a momentary outage, the source current of the pfc- on pin starts to increase. as the voltage on the pfc-on pin becomes low, the amount of current increases. since the external resistor is connected to gnd, the voltage on the pfc-on pin is balanced between the source current and the voltage determined by the resistance. this functio n prevents increase of ac current right after ac-voltage input is resumed. full-wave rectified ac pfc-on delay out pfc output voltage ipfc-on 0.79v 0.82v 1.2v figure 6 pfc hold function operation waveform 1 the hold time for pfc operation is adjusted by the value of the capacitance on the delay pin. note, however, that if vcc voltage of the ic is not normally supplied during a momentary outage, the pfc-on hold function does not operate.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 19 of 40 (2) when the momentary outage is long when the momentary outage is long enough that the delay pin voltage reaches 1.2 v, out is stopped and ss is reset, then pfc operation is stopped. the current on the pfc-on pin switches from source current to sink current and the voltage on the pfc-on pin falls. when the supply of ac voltage resumes, the ic is restarted in a soft-start operation. 0.79v 0.82v full-wave rectified ac pfc-on delay out pfc output voltage ipfc-on soft start ss 1.2v figure 7 pfc hold function operation waveform 2 note: when the pfc output voltage is driving a heavy load, the pfc output voltage falls rapidly, and the fb pin may fall below 0.52 v before the delay pin reaches 1.2 v. here, the out pin is stopped, and the ss pin is reset by the fb pin low-voltage detection circuit.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 20 of 40 5. fb pin function the fb pin is a feedback input for the pfc output voltage. this pin is applied to voltage divided pfc output with resistors. the pfc output voltage is controlled so that the voltage on fb becomes 2.5 v. the fb pin function provides protection against abnormal pfc output voltages. the protective functions include overvoltage detection and low- voltage detection. these functions do not operate when vref voltage is lower than 4 v as uvl operation and shutdown state. 680k fb ss pfc output voltage 0.47 vref 25 a vref fb control eo 0.033 820k b+ovp fb-low 2.688v 2.638v 2.5v v-amp 0.50v 0.52v 14 1 5 15 gate driver +/? 1.0a(peak) to power mos fet gate out figure 8 internal circuits connected to the fb pin
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 21 of 40 5-1. power-supply startup operation when the ac voltage is applied, the pfc-on pin voltage starts to rise up. after it has reached 0.82 v, the voltage on the ss pin starts to be discharged and pfc operation is star ted with the soft-start function. once the pfc operation is started, the voltage on the fb pin rises and is controlled so that it reaches 2.5 v. full-wave rectified ac pfc-on ss cao ss cao fb 0.82v 2.5v pfc output voltage figure 9 waveform in startup operation 5-2. operation when the power-supply stops when the supply of ac voltage stops, both of the pfc output voltage and the voltage on the fb pin fall. when the voltage on the fb pin is lower than 0.52 v, the pfc operation stops and the ss pin is reset. full-wave rectified ac fb ss 0.52v out figure 10 waveform in stop operation note: when the pfc output voltage is driving light load, the pfc output voltage falls slowly, and the pfc-hold function may be activated before the voltage on the fb pin falls to 0.52 v. in this case, the pfc hold function operates, stopping output on the out pin and resetting the ss pin.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 22 of 40 5-3. overvoltage operation when the pfc output voltage is larger th an 7.5% of the prescribed voltage due to an abnormality in the system or a sudden change of ac voltage or load, operation of the out pin is stopped. when the pfc output voltage returns to within 5.5% of the prescribed voltage, operation of the out pin is resumed. out fb pfc output voltage 107.5% of the output voltage 105.5% of the output voltage 2.688v 2.668v figure 11 waveform of operation after overvoltage detection by the fb pin
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 23 of 40 6. ic shutdown function when the delay pin is pulled up to 4 v, the ic shutdown function operates. during shutdown, the ic enters the standby state. to reset the ci rcuit from the shutdown state, the voltage on vcc must be lowered to 4 v or less. after this reset, when the vcc pin voltage reaches 10.5 v, the ic is restarted. latched state vcc delay vref 4v 4.0v 10.5v internal latch 9v figure 12 waveform of operation in ic shutdown
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 24 of 40 main characteristics 0 50 100 150 200 250 012345678910 11 power dissipation vs. power supply voltage characteristics 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 10 12 14 16 18 20 22 24 is ( a) icc (ma) vcc (v) standby current vs. power supply voltage characteristics vcc (v) ta = 25c ta = 25c cl = 1000pf
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 25 of 40 4.8 4.85 4.9 4.95 5 5.05 5.1 5.15 5.2 ?40 ?20 0 20 40 60 80 100 120 operating frequency temperature characteristics 55 57 59 61 63 65 67 69 71 73 75 ?40 ?20 0 20 40 60 80 100 120 frequency (khz) vref (v) ta (c) ta (c) reference voltage temperature characteristics vcc = 12v iref = ?1ma vcc = 12v rt= 27k ct = 1000pf
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 26 of 40 9.5 9.7 9.9 10.1 10.3 10.5 10.7 10.9 11.1 11.3 11.5 ?40 ?20 0 20 40 60 80 100 120 8.4 8.6 8.8 9 9.2 9.4 9.6 vh (v) ta (c) ?40 ?20 0 20 40 60 80 100 120 ta (c) start-up voltage temperature characteristics shutdown voltage temperature characteristics vl (v)
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 27 of 40 120 140 160 180 200 220 240 260 280 3 3.5 4 4.5 5 5.5 6 6.5 7 is ( a) ?40 ?20 0 20 40 60 80 100 120 ta (c) ?40 ?20 0 20 40 60 80 100 120 operating current temperature characteristics ta (c) standby current temperature characteristics vcc = 9.5v icc (ma) vcc = 12v cl = 0pf
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 28 of 40 0 50 100 150 200 250 0 100 200 300 400 600 500 ta = 25c vcc = 12v veo = veoh rt = 27k iac pin current ( a) cai pin current vs. iac pin current characteristics cai pin current (a) pfc-on = 0.5v pfc-on = 5v pfc-on = 4v pfc-on = 3v pfc-on = 2v pfc-on = 1v
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 29 of 40 precautions on usage figure 13 shows symbols which are used in this chapter. rcs rmo imo isum cgnd cai rmo l cpfc rcao1 rac rmo rcs 1000p cao climit vcc ss eo fb iac pfc-on ct rt out gnd delay cgnd cai vref cdelay 0.1 ct rt css 10 12v rclimit1 rclimit2 vout vout ac_rectifier rpfc1 rpfc2 rfb1 rfb2 reo1 reo2 ceo1 ceo2 rmo ccao1 rcao2 ccao2 r2a20111 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9 rclimit3 cclimit1 rref-cai figure 13 template illustrating symb ols of external circuit elements
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 30 of 40 1. power limit function 1-1. limited power value when the load exceeds the rated load, the power is limited by the set power value and the ic enters the constant power control state. this indicates that the power is limited by nearly-constant power independent of the input ac voltage, compared to the conventional overcurrent detection circuit. the limited power value is determined by the values of external resistors and is expressed by the following equation: r cs ? r ac ? r pfc2 2 r mo ? (r pfc1 + r pfc2 ) 2 p limit = 1.74 ? this is the equation for reference only. be sure to sufficien tly confirm the operation by using the actual circuit board. the actual value may differ from the equation by conditions, but the trend indicated by the equation remains the same (for instance, as the amount of rmo becomes large, the limited power value increases). therefore, use the equation above for reference to fine-tune the resistance values. 1-2. trend of limited power value for input ac voltage although the limited power value is nearly constant with respect to the input ac voltage, it may be deviated to a certain degree from linearity by conditions. when it has a negative sl ant with respect to the input ac voltage, add a resistor between the cai pin and the vref pin so that the devi ation from linearity can be corrected to some degree. 1-3. limit on constant power function after the pfc power supply enters the constant power operati on state and load increases further, the pfc output voltage reaches about 2 input ac voltage. at this point the pfc output voltage is unable to fall below the point in principle of the boost converter. if the load increases further at this po int, current increases on the peak part of input current, then the power starts increasing again. this current cannot be controlled by the ic. pfc output current pfc output current pfc output voltage pfc output power 2 vac constant power curve rise in power fo r the reason that the ac voltage is high and the output voltage is unable to fall below 2 vac. figure 14 outline of constant power limit function 1-4. effects on power limit characteristics of resistor rcao1 of cao pin as the external resistance rcao1 of the cao pi n is small, the limited power value decreases. this decrease is caused by rise of the voltage on the eo pin in principle as rcao1 becomes small. when the load becomes heavy and the voltage on the eo pin is clamped at the upper limit, the ic is operated in the power limit operation mode. therefore, since the voltage on eo pi n increases, the power limit value decreases relatively.
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 31 of 40 1-5. relations between rt resistor and power limit the maximum current on the cai pin is expressed in invers e proportion to the resistance of the rt pin as 4.7/rt. since imo is proportional to the input ac current, when the value of ac voltage drops, imo rises. imo is, however, limited by the above maximum current value. if the value of imo (max.) is set higher than the required current value with the minimum input ac voltage, the power limit function is operated in all range of input ac voltage without any difficulty. if the value of imo (max.) is smaller than the required current, the rated power can not load (see figure 15). rated powe r limit power range of input ac voltage rt increases power area where the rated power cannot load imo rt increases figure 15 rt and power limit in case of sudden turn from low ac voltage to high ac voltage as in return from a momentary outage or sag, the voltage on the pfc-on pin changes after the ac voltage for its smoothing capacitance. therefore, the voltage on the pfc-on pin remains low while the ac voltage is high. in such a state, the current is controlled to increase transiently (see figure 16). the overcurrent detectio n circuit is operated due to this increas e in current, and noise of an inductor may be generated. in this case, set the limitation on current by adjusting the rt pin resistance to prevent the operation of overcurrent detection circuit. full-wave rectified ac pfc-on pin ac current figure 16 increase in current due to ac voltage sag
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 32 of 40 1-6. tolerance of limited power values the tolerance of the limited power values depend on the tole rance of the cai pin current. since overcurrent detection value is constant, set the rt resistance as illustrated in figur e 17, so that the resistance does not exceed the overcurrent detection level. seen in figure 17, th e key to select a switching device is not the tolerance in the limited power value but in the current value limited by rt. the tolerance of this current ranges from ? 10% to + 10%. rated power limited power power input ac voltage isum (peak) limited power value in case of only the overcurrent protection overcurrent detection level current limited by rt figure 17 overcurrent detection level and power limitation
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 33 of 40 2. operation of pfc on/off function pfc function of the r2a20111 can be turned on and off externally using the following methods. (1) pull down the voltage on the pfc-on pin to the gnd level. (2) pull up the voltage on the ss pin to the vref voltage level. (3) pull down the voltage on the climit pin to 1.3 v or lower. (4) pull up the voltage on the delay pin to 4 v or more. since the voltage on the out pin is fixe d to the gnd level in each case, the boost operation is halted. the sections from 2-1 to 2-4 describe phenomena which may occur for functional reasons of the ic. make sure to sufficiently confirm each operation using the actual th e power-supply board. when the curre nt flows transiently and noise of an inductor is generated, refer to section 1-5 ?relations between rt resistor and power limit?. 2-1. on/off operation by using the pfc-on pin when the voltage on the pfc-on pin drops, the ic controls to increase the ac current. th erefore, the ac current is controlled to increase while the voltage on the pfc-on pin is pulled down. furthermore, the pfc-on pin has the pfc hold function. since the pfc operation is not halted during the hold periods, the control current increases during this period (see figure 18). also, when the pfc function is turn ed off in the light load, the output voltage may rise due to this increase current. pfc hold time 0.79v 0.82v 0v pfc-on pin delay pin 1.2v ac current soft start full-wave rectified ac figure 18 on/off operation by pfc-on pin
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 34 of 40 2-2. on/off operation by using the ss pin when the voltage on the ss pin is pulled up to the vref volta ge level, the voltage level of the cao pin is also pulled up together with the ss pin. then, the out pin is stopped. after the voltage level of the ss pin is pulled up, a few pulses on the out pin may be generated by capacitance of the phase-compensation circuit of the cao pin (see figure 19). the circuit to directly pulls up the cao pin is not recomm ended since the circuit may a ffect the phase-compensation circuit of the current amplifier. ss pin voltage cao pin voltage out pin voltage figure 19 on/off operation by pulling up ss pin 2-3. on/off operation by using the climit pin when the voltage on the climit pin falls to 1.3 v or lower, the pulses on the out pin stop by the overcurrent detection circuit. when the voltage of the climit pin is released, the pulses on the out pin is resumed without soft start. 2-4. on/off operation by using the delay pin when the voltage on the delay pin is pulled up to 4 v or more, the ic enters the shutdown state and the pulses on the out pin is stopped. since the shutdown function is operated in latch mode, the ic is not resumed even when the voltage level of the delay pin is pulled down. the ic resumes only when lower the voltage on the vcc pin to 4 v or lower once and raise the voltage on the vcc pin higher than the uvl voltage. figure 20 illustrates an example of detection circuit. vref pfc output voltage delay pin 1 2 4 3 5 m51958bl gnd figure 20 example of shutdown circuit
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 35 of 40 3. overcurrent detection circuit when the rc filter is added the climit pin to prevent noise er rors (see figure 21), the cut-off frequency shifts on the lower frequency side than the added rc filter because of th e rclimit 1 and rclimit 2. this causes possibility that exactly current can not detect. rclimit2 c climit rclimit1 r vref rcs figure 21 example of climit pin filter since the overcurrent is detected by coil current, the detected current value is not the same as the peak value of the ac input current (see figure 22). because of this difference, the overcu rrent detection circuit is operated before the power reaches the constant power limit, and noise of an inductor may occur. in such a case, raise the overcurrent detection level. ac input current peak overcurrent detection level coil current i difference in current is approximated by the following equation: vac: input ac voltage l: step-up coil inductance d: ic out pin on duty fosc: ic operating frequency 2 vac d fosc 2 l i = figure 22 ac input current and coil current
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 36 of 40 4. pfc hold function the pfc hold time can be adjusted by changing the valu e of the capacitor connected to the delay pin. the capacitance is charged with the source current from the ic and the pfc hold function is operated until the voltage on the delay pin reaches 1.2 v. althou gh the pfc-on pin detects an occurr ence of the momentary outage, the detection delay time occurs because a smoothing capacitor is connected to the pfc-on pin. this delay time depends on the value of a resistor and the value of a smoothing capacitor which are connected to the pfc-on pin. therefore, the hold time is dependent on the following: (a) value of the capacitor connected to the delay pin (b) current value of the delay pin (c) values of the resistor and the capacitor connected to the pfc-on pin actual pfc hold time thold is expressed in the following equation (see figure 23): r pfc1 + r pfc2 r pfc2 v pfc-on = ? 4.7 v r t i src-delay = r pfc1 + r pfc2 r pfc1 ? r pfc2 t3 = ? c pfc ? ? in 1.2 v i src-delay t2 + t3 = c delay ? 0.79 v v pfc-on t1 = ? r pfc2 ? c pfc ? in thold = t1 + t2 ? t3 0.4 v ? 2 ? 2 ? v ac 0.82 v ? 2 ? 2 ? v ac 2 ? 2 ? v ac 0.79v 0.82v 0.4v t1 t2 t3 thold full-wave rectified ac pfc-on pin delay pin 1.2v figure 23 pfc hold time
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 37 of 40 5. precautions on pins 5-1. out pin undershoot may occur on the pwm pulse of the out pin because of a parasitic inductance of wiring, etc. this undershoot (negative electric potential) may cau se errors of the ic. in such a case, use a schottky barrier diode, etc. to suppress the undershoot. 5-2. delay pin when the voltage on the delay pin reaches 4 v or more, th e shutdown function is operat ed and the ic enters the shutdown state. since the shutdown state is in latch mode, the ic is not resumed unless the voltage on the vcc pin is, once, lowered to 4 v or below. when the pfc hold function is not used, lower the delay pin capacitance as possible. however, connect a capacitor with a few thousands pf or more capac itance to the delay pin so that the shutdown function will not be operated due to noise, etc. and note wiring pattern not to catch the noise. 5-3. cai pin and climit pin these pins are connected to a cu rrent detection resistor via a resistor. provide a rush-current protection circuit, not to exceed the maximum rating because of the rush current at the startup of power supply. 5-4. vref pin the voltage on the vref pin is a reference voltage in the ic. for stabilizing the voltage on the vref pin, be sure to connect a capacitor between the vref pin and gnd. howe ver, in capacitance of a capacitor to be connected, overshoot may occur at the rising of the vref pin (see figure 24). pay special attention to this point when the voltage on the vref pin is used as the power supply fo r an external circuit and a reference voltage. furthermore, note that the source current of the vref pin will not exceed the maximum rating. vref overshoot 5 5.5 6 6.5 7 0.01 0.1 1 cref ( f) vref peak voltage (v) figure 24 overshoot amount on vref pin (reference data)
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 38 of 40 6. pattern layout in designing the pattern layout, pay as much attention as is possible to the following points. (1) place the ic pins (particularly, cgnd, cai, pfc-on, iac, fb) and their wiring as far from high -voltage switching lines (particularly the drain voltage for the power mosfet) as possible and in general design the wiring to minimize switching noise. (2) wiring between cgnd and rcs via rmo and wiring between cai and rcs via rmo connect nearly and separately to rcs. (3) it is probable that stability operation is achieved by inputting signals via low pass filter to climit, pfc-on, iac, fb terminal. (4) place a resistors and capacitors connect vref , rt, cao, ct, vcc as close to the ic as possible, and keep the wiring short. (5) pattern layout priority (for reference) 1. place the ic as far from high vo ltage switching lines as possible. 2. the pattern of the gnd should be as wide as possible. 3. place the stabilizing capacitor for vref as close to the ic as possible. 4. place the stabilizing capacitor for v cc as close to the ic s possible. 5. place the resistors and capacitors (rcao1, rcao2, ccao1, ccao2) for ca o as close to the ic as possible. 6. wiring between cgnd and rcs via rmo and wiring between cai and rcs via rmo connect nearly and separately to rcs. 7. place the timing resistor for rt as close to the ic as possible. 8. place the timing capacitor for ct as close to the ic as possible. 9. place the resistors and capacitors (reo1, reo2, ce o1, ceo2) for eo as close to the ic as possible. 10. place the resistors and capacitors (rpfc1, rpfc2, cpfc) for pfc-on as close to the ic as possible. 11. place the resistors (rfb1, rfb2) for fb as close to the ic as possible. 12. place the resistors (rac) for iac as close to the ic as possible. 13. place the resistors (rclimit1 , rclimit2) for climit as close to the ic as possible. 14. place the capacitor (cdelay) for delay as close to the ic as possible. 15. place the capacitor (css) for ss as close to the ic as possible. cpfc rac rmo rcs 1000p cao climit vcc ss eo fb iac pfc-on ct rt out gnd delay cgnd cai vref cdelay 0.1 ct rt css 10 12v rclimit1 rclimit2 vout ac_rectifier rpfc1 rpfc2 rfb1 rfb2 reo1 reo2 ceo1 ceo2 rmo r2a20111 2 1 3 4 5 6 7 8 15 16 14 13 12 11 10 9 rcao2 rcao1 ccao2 ccao1
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 39 of 40 (6) there is a potential that placing the heat sink betwee n ics and power mosfet will be a some kind of shield and reduce the radiation noise (figure 25). f e t ic f e t ic heat sink heat sink figure 25 example of layout of parts
R2A20111SP/dd rej03f0231-0100 rev.1.00 mar 28, 2007 page 40 of 40 package dimensions 0.80 0.15 1.27 7.50 8.00 0.40 0.34 a 1 10.5 max nom min dimension in millimeters symbol reference 2.20 0.90 0.70 0.50 5.50 0.20 0.10 0.00 0.46 0.25 0.20 0.15 7.80 8 0 0.12 1.15 10.06 l 1 z h e y x c b p a 2 e d b 1 c 1 e l a *1 *2 e 8 1 16 9 xm p *3 y f index mark b d e h z a terminal cross section ( ni/pd/au plating ) p c b 1 1 detail f l l a note) 1. dimensions"*1 (nom)"and"*2" do not include mold flash. 2. dimension"*3"does not include trim offset. e p-sop16-5.5x10.06-1.27 0.24g mass[typ.] fp-16dav prsp0016dh-b renesas code jeita package code previous code 7.62 max nom min dimension in millimeters symbol reference 19.2 6.3 5.06 a 1 z b 3 d e a b p c e l e 1 0.51 0.56 1.30 0.19 0.25 0.31 2.29 2.54 2.79 0 15 20.32 7.4 0.40 0.48 1.12 2.54 1 p 1 3 1 8 16 9 e b a l a z e c e d b 0.89 ( ni/pd/au plating ) p-dip16-6.3x19.2-2.54 1.05g mass[typ.] dp-16fv prdp0016ae-b renesas code jeita package code previous code
notes: 1. this document is provided for reference purposes only so that renesas customers may select the appropriate renesas product s for their use. renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of renesas or any third party with respect to the information in this document. 2. renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of t he use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. you should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. when exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. all information included in this document such as product data, diagrams, charts, programs, algorithms, and application ci rcuit examples, is current as of the date this document is issued. such information, however, is subject to change without any prior notice. before purchasing or using any renesas products listed in this document, please confirm the latest product information with a renesas sales office. also, please pay regular and careful attentio n to additional and different information to be disclosed by renesas such as that disclosed through our website. (http://www.renesas.com ) 5. renesas has used reasonable care in compiling the information included in this document, but renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. when using or otherwise relying on the information in this document, you should evaluate the information in light of the t otal system before deciding about the applicability of such information to the intended application. renesas makes no representations, warranties or guaranties regarding th e suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this do cument or renesas products. 7. with the exception of products specified by renesas as suitable for automobile applications, renesas products are not desi gned, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of h uman injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion co ntrol, aerospace and aeronautics, nuclear power, or undersea communication transmission. if you are considering the use of our products for such purposes, please contact a r enesas sales office beforehand. renesas shall have no liability for damages arising out of the uses set forth above. 8. notwithstanding the preceding paragraph, you should not use renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to us e renesas products in any of the foregoing applications shall indemnify and hold harmless renesas technology corp., its affiliated companies and their officers, dir ectors, and employees against any and all damages arising out of such applications. 9. you should use the products described herein within the range specified by renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. renesas sha ll have no liability for malfunctions or damages arising out of the use of renesas products beyond such specified ranges. 10. although renesas endeavors to improve the quality and reliability of its products, ic products have specific characteristic s such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. please be sure to implement safety measures to guard against the poss ibility of physical injury, and injury or damage caused by fire in the event of the failure of a renesas product, such as safety design for hardware and software includin g but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. among others, sinc e the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. in case renesas products listed in this document are detached from the products to which the renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. you should implement safety measures so that renesas products may not be easily detached from your products. renesas shall have no liability for damages arising out of such detachment. 12. this document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from r enesas. 13. please contact a renesas sales office if you have any questions regarding the information contained in this document, renes as semiconductor products, or if you have any other inquiries. sales strategic planning div. nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan http://www.renesas.com refer to " http://www.renesas.com/en/network " for the latest and detailed information. renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500, fax: <1> (408) 382-7501 renesas technology europe limited dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, u.k. tel: <44> (1628) 585-100, fax: <44> (1628) 585-900 renesas technology (shanghai) co., ltd. unit 204, 205, aziacenter, no.1233 lujiazui ring rd, pudong district, shanghai, china 200120 tel: <86> (21) 5877-1818, fax: <86> (21) 6887-7898 renesas technology hong kong ltd. 7th floor, north tower, world finance centre, harbour city, 1 canton road, tsimshatsui, kowloon, hong kong tel: <852> 2265-6688, fax: <852> 2730-6071 renesas technology taiwan co., ltd. 10th floor, no.99, fushing north road, taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology singapore pte. ltd. 1 harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas technology korea co., ltd. kukje center bldg. 18th fl., 191, 2-ka, hangang-ro, yongsan-ku, seoul 140-702, korea tel: <82> (2) 796-3115, fax: <82> (2) 796-2145 renesas technology malaysia sdn. bhd unit 906, block b, menara amcorp, amcorp trade centre, no.18, jalan persiaran barat, 46050 petaling jaya, selangor darul ehsan, malaysia tel: <603> 7955-9390, fax: <603> 7955-9510 renesas sales offices ? 2007. renesas technology corp., all rights reserved. printed in japan. colophon .7.0

▲Up To Search▲

Price & Availability of R2A20111SP

	To Download R2A20111SP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .